module MEMWB(
    input clk, rst, 

    input MEM_RegW, 
    output reg WB_RegW, 

    input [1:0] MEM_Mem2R, 
    output reg [1:0] WB_Mem2R, 

    input [4:0] MEM_gprWeSel, 
    output reg [4:0] WB_gprWeSel, 

    input [31:0] dm_out, 
    output reg [31:0] WB_dm_out, 

    input [31:0] MEM_aluDataOut, 
    output reg [31:0] WB_aluDataOut, 

    input [31:0] MEM_PC, 
    output reg [31:0] WB_PCPLUS4
);

    always @(posedge clk, posedge rst)
    begin
        if (rst)
        begin
            WB_aluDataOut = 0;
            WB_dm_out = 0;
            WB_gprWeSel = 0;
            WB_Mem2R = 0;
            WB_RegW = 0;
            WB_PCPLUS4 = 0;
        end

        else
        begin
            WB_aluDataOut = MEM_aluDataOut;
            WB_dm_out = dm_out;
            WB_gprWeSel = MEM_gprWeSel;
            WB_Mem2R = MEM_Mem2R;
            WB_RegW = MEM_RegW;
            WB_PCPLUS4 = MEM_PC + 4;
        end
    end

endmodule